1. Field of the Invention
This invention relates generally to a semiconductor integrated circuit formed on an SOI substrate and, more particularly, to a semiconductor integrated circuit having a static electricity protection transistor formed on an SOI film over a substrate, and to a method for manufacturing the same.
2. Background Information
There is shown in FIG. 7 a conventional static electricity protection transistor formed on a substrate having an SOI film. Meanwhile, FIG. 8 shows a connection diagram thereof. FIG. 7A is a plan view as viewed from above FIG. 7B a sectional view taken on line (axe2x80x94a) in a gate width direction, and FIG. 7C a sectional view taken on line (bxe2x80x94b) in a gate lengthwise direction. The conventional static electricity protection transistor is structured by a gate electrode 43, a gate oxide film 40, a channel region 57, a source region 41, a drain region 42, a ground region 56, an interconnect contact, metal interconnections 58, 59, 60, and an interlayer insulation film 46. As shown in the figure, the gate oxide film 40 is formed on the SOI film as a channel region. The gate electrode 43 is formed of polysilicon on the channel region 57, on which the interlayer insulation film 46 is formed. Here, the static electricity protection transistor basically uses an N-type MOS transistor and hence the channel region SOI film is in a P-type. In some cases, a P-type transistor is employed. On an SOI wafer with a thin SOI film thickness, the source region 41, drain region 42 and ground region 56 in depth direction reach the insulation film 2 on the substrate 1. LOCOS 45 is formed in areas other than the channel region 57, source region 41, drain region 42 and ground region 56. The LOCOS 45 reaches the insulation film 2 over the substrate 1. Consequently, this LOCOS 45 completely separates the channel region 57, source region 41, drain region 42 and ground region 56 from the channel region, source region, drain region and ground region of another transistor.
As shown in FIG. 8, in the conventional static electricity protection transistor a pad 47 is connected to the drain region 42 of the static electricity protection transistor. The drain 42 is in turn connected to a semiconductor integrated circuit (semiconductor circuit). The source region of the static electricity protection transistor is connected to a ground terminal of the semiconductor integrated circuit. Here, for a static electricity protection transistor formed on an SOI film over a substrate through an insulation film, a gate electrode 43 is connected to a ground terminal through a resistance 48. Also, if a static electricity protection transistor is formed on an SOI film in a same layout as that of a static electricity protection transistor formed on a bulk wafer, a gate electrode 43 will be in floating. The source region 41 is connected to the ground region 56 and ground terminal. Here, the ground region 56 formed on the SOI wafer is not electrically connected to the channel region 57 and substrate 1, differently from a transistor formed on a bulk wafer. Consequently, the channel region 57 is floating in potential.
Furthermore, a method for manufacturing a conventional static electricity protection transistor is explained with reference to FIGS. 9(A)-9(E), 10(A)-10(E) and 11(A)-11(C). An SOI film 19 is formed over a substrate 1 through an insulation film 2 (FIG. 9A). An oxide film 50 is formed on the SOI film 19 (FIG. 9B). Next, the oxide film 50 is patterned to form openings 51 for alignment marks (FIG. 9C). This is placed in a thermal oxidation furnace to form a thermal oxide film 52 (FIG. 9D). At this time, the SOI film silicon positioned at the openings 51 of the oxide film 50 is oxidized greater than the SOI film silicon having the oxide film 50. Consequently, a thermal oxide film 52 at the opening 51 is greater in thickness than other portions. If the thermal oxide film 52 is removed, recess steps are formed as shown in FIG. 9E which are alignment marks 53. Then, an oxide film 54 and nitride film 55 for LOCOS are formed and patterned (FIG. 10A). After patterning the nitride film 55, LOCOS 45 is formed in an oxide furnace as shown in FIG. 10B.
Next, the nitride film 55 and the oxide film 54 in areas other than the LOCOS 45 are removed, and thereafter a gate oxide film 40 is formed (FIG. 10C). Furthermore, the polysilicon film is formed and patterned to form a gate electrode 43 (FIG. 10D). Then, as shown in FIG. 10E, N-type ions are implanted to the source/drain region 41, 42. Further, as shown in FIG. 11A, P-type ions are implanted to a ground region 56. Next, as shown in FIG. 11B an interlayer insulation film 46 is formed. Thereafter, contact holes are formed and then the interlayer insulation film 46 is planarized by a reflow process, followed by forming metal interconnections 58, 59, 60 as shown in FIG. 11C. A static electricity protection transistor thus formed is connected as shown in FIG. 8.
In the conventional static electricity protection transistor constructed as above, when static electricity enters the pad, surface breakdown occurs between the drain and the substrate to flow charges toward the substrate being in a ground level. The flowing charges to the substrate raises a potential on the substrate to thereby induce bipolar operation between the drain region, the channel region and the source region. Thus, current flows through a path of the drain, the substrate and the source.
In the static electricity protection transistor formed on a bulk wafer, a substrate contact is provided around the static electricity protection transistor, thereby bringing a substrate potential to a ground level. However, a transistor is formed on an SOI wafer having a small semiconductor film thickness on an insulation film thereof by the conventional CMOS forming method, and the SOI film in a depth direction will be entirely formed as a source/drain region. Consequently, even if a substrate contact is provided around the transistor as in the conventional transistor, the potential of the channel region (or substrate potential) is in a floating condition. Due to this, the charge flowing to the channel region of the static electricity protection transistor due to surface breakdown has nowhere to exit, resulting in an abrupt increase in the channel region potential. Bipolar operation, if induced herein, is satisfactory. However, if a large amount of chargers [more in amount] enter the channel region, there arises a problem that electrostatic breakdown or Joule thermal breakdown possibly occurs because that region is very small in size and hence low in capacitance for accepting charges.
Meanwhile, where bipolar operation occurs through the drain region, channel region and source region, the static electricity protection transistor formed on a bulk wafer has a source connected to a substrate ground region so that the charges entered the source region can be released toward the substrate. However, in the static electricity protection transistor formed on an SOI wafer having an small SOI film thickness on an insulation film, a source region is directly connected to a ground terminal of a semiconductor integrated circuit. Accordingly, the charges entered the source region have nowhere to escape so that there is a possibility that they flow to other transistors connected to the ground line and induce electrostatic breakdown.
Furthermore, where bipolar operation occurs through the drain region, channel region and source region to flow large current through the transistor, large heat generation occurs on the transistor. In the conventional transistor formed on a bulk transistor, because the transistor at its lower side is connected with a substrate, heat dissipates through the substrate. On the SOI wafer, however, the transistor at its lower side is covered by an oxide film that is poor in thermal conductivity. Consequently, the amount of heat generated upon flowing current through the transistor is greater than that in the transistor formed on a bulk wafer, resulting in a problem of inducing thermal breakdown.
Meanwhile, there is also a problem on a way to ground the gate of the static electricity protection transistor. The gate electrode of the static electricity protection transistor on a bulk wafer is grounded to the substrate through a resistance. This is because, if the gate be connected directly to a ground line, the charges released onto the ground line enter the gate of the static electricity protection transistor thereby causing gate breakdown. However, if a static electricity protection transistor is formed on an SOI wafer to a same layout as that of a bulk wafer, its gate electrode is in a floating state. If in this state static electricity or the like enters the pad, no surface breakdown occurs because of unstable gate potential so that current flows due to punch-through. However, because there is limitation in amount of current to flow due to punch-through, it is impossible to completely release the static electricity entered the pad. Thus, there has been a problem that it results in breakdown in an internal circuit.
In order to solve the above problems, in a semiconductor integrated circuit having a static electricity protection transistor according to the present invention, the static electricity protection transistor comprises: a source region; a drain region; a channel region; a gate electrode provided on the channel region through a gate oxide film; a substrate contact formed penetrating through the SOI film and reaching part of the substrate; a substrate connection region contact connecting between the channel region and the substrate contact; and an interconnection provided to the substrate contact and the substrate connection region contact and electrically connecting between the channel region and the substrate. With this structure, the charges flowing into the channel region of the static electricity protection transistor are allowed to flow through the substrate contact onto the substrate. Thus, prevention is made against electrostatic breakdown or Joule thermal breakdown.
Further, at least one is further comprised of a low resistance connection region formed in a surface of the substrate in a position provided with the substrate contact and having a resistance lower than that of the substrate and a low resistance connection region formed in the SOI film in a position provided with the substrate connection region contact and having a resistance lower than that of the SOI film. This makes the connection between the channel region and the substrate lower in resistance with positiveness.
Further, the substrate connection region contact is arranged surrounding the substrate contact and including the substrate contact.
Further, a contact region formed from an SOI film the same as in the channel region is provided, a gate oxide film is formed on the contact region, and a gate electrode is formed only on a part of the gate oxide film. That is, in the connection region there exist a portion formed with the gate electrode through the gate oxide film and a portion not formed with it. With this structure, it is possible to prevent the connection region from being implanted with an ion species for the source/drain region during an ion implant process for forming a source/drain region.
Also, a static electricity protection transistor comprising: a source region; a drain region; a channel region; a gate electrode provided on the channel region through a gate oxide film; an interlayer insulation film provided on the gate electrode; an interconnect contact hole provided on the source region and penetrating through the interlayer insulation film and the gate oxide film; a substrate contact penetrating through the interlayer insulation film and the SOI film and reaching part of the substrate; and an interconnection provided to the interconnect contact hole and the substrate contact and electrically connecting between the source region and the substrate. With this structure, the charges entered the source region are released onto the substrate through the substrate contact. This eliminates the possibility that the charges flow to other transistors connected to a ground line thereby inducing electrostatic breakdown.
Also, a method for manufacturing a semiconductor integrated circuit comprises: a step of forming an oxide film on an SOI film over a substrate; a step of forming a contact hole penetrating through the oxide film and the SOI film and reaching part of the substrate; a step of forming a LOCOS; a step of forming a gate oxide film; a step of forming a gate electrode; a step of removing the gate oxide film from part of a side surface and part of a bottom surface of the contact hole; and a step of forming a metal interconnection to electrically connect between the SOI film and the substrate.
Also, a method comprises: a first step of forming an oxide film on an SOI film over a substrate; a second step of forming a contact hole penetrating through the oxide film and the SOI film and reaching part of the substrate; a third step of forming a LOCOS; a fourth step of forming a gate oxide film in other areas than the LOCOS; a fifth step of forming a gate electrode on the gate oxide film; a sixth step of decreasing resistance of the SOI film and the substrate in a portion around the contact hole to form a first low resistance connection region and a second low resistance connection region; a seventh step of removing the gate oxide film from part of a side surface and part of a bottom surface of the contact hole to expose the first low resistance connection region and the second low resistance connection region; and an eighth step of electrically connecting between the first low resistance connection region and the second low resistance connection region.
Here, an insulation film may be provided on the substrate and an SOI film be provided thereon. Also, in the second step an alignment hole is simultaneously formed penetrating through the oxide film and SOI film and reaching part of the substrate. In the third step LOCOS is formed reaching the insulation film by exposure with reference to the alignment hole. In the sixth step ion implantation is made to the SOI film and substrate in positions around the contact hole to reduce the respective portions, forming a first low resistance connection region and a second low resistance connection region. Furthermore, after the sixth step, an interlayer insulation film is formed. In the seventh step the gate oxide film is removed from part of a side surface and part of a bottom surface of the contact hole to expose the first low resistance connection region and the second low resistance connection region.